1. Field of the Disclosure
The present invention relates to flat display devices and method of fabricating the same, and more particularly to a flat display device which can make narrow bezel design easy and minimize resistance variation between adjacent link lines for improving a picture quality.
2. Discussion of the Related Art
Recently, many flat display devices are used as the display devices owing to their features of excellent picture quality, light, thin, and low power consumption. In the flat display devices, there are liquid crystal display devices, organic light emitting diode display devices, and the like, most of which are put into commercial use and come into market.
In the meantime, in order to provide a picture display area as large as possible in comparison to a size of the device, a small sized flat display device applied to a portable terminal, a notebook computer or so on requires a technology for making an area (a bezel area) excluding the picture display area smaller. Accordingly, the small sized flat display device has a gate driving unit and a data driving unit put into one integrated circuit, that are provided individually in a medium to large sized flat display device. That is, the small sized flat display device has all of the gate driving unit and the data driving unit integrated into a driving IC.
According to this, the driving IC has gate output terminals each for supplying a scan signal, and data output terminals each for supplying a data signal. The driving IC is connected to a picture display unit through a plurality of gate link lines and a plurality of data link lines, electrically. In this instance, the plurality of gate link lines connect the gate output terminals to the plurality of gate lines and the plurality of data link lines connect the data output terminals to the plurality of data lines.
In the meantime, in order to make the bezel area narrow, the related art flat display device has a dual link structure applied to the gate link lines provided on both sides of the picture display unit. The gate link lines of the dual link structure has a structure in which adjacent gate link lines are formed on layers different from each other. For an example, odd numbered gate link lines are formed as gate line metals at a first layer, and even numbered gate link lines are formed as gate line metals at a second layer which is a layer different from the first layer. The flat display device having the dual link structure applied thereto can make a width between the gate link lines small, enabling to design a width of the bezel area narrow, at the end.
However, the flat display device having the dual link structure applied thereto has the following problem. That is, since the odd numbered gate link lines and the even numbered gate link lines are formed on layers different from each other, a process variation is accompanied, in which thicknesses or line widths of the lines are formed different from one another. The process variation causes a great resistance variation between adjacent gate link lines, affecting the scan signal transmitted through the gate link lines making a picture quality poor.